Non-Patent Documents 1 and 2 describe pipelined analog/digital converters (ADC) in which a multiplication type D/A converter (MDAC) including a switched capacitor circuit is used at each stage of the analog/digital converter. Further, these analog/digital converters include capacitors, and mismatches inevitably occur among the capacitors. Non-Patent Documents 1 and 2 describe techniques for canceling these mismatches.
Non-Patent Document 3 describes a technique for correcting mismatches among capacitors used at each stage of an analog/digital converter after an input analog signal has been converted into a digital value.
Patent Document 1 describes a multistage analog/digital converter (ADC) in which capacitor mismatch is corrected digitally. Patent Document 2 describes a pipelined A/D conversion circuit capable of correcting gain errors at each stage and suppressing deterioration of a linearity characteristic. Patent Document 3 describes an A/D converter exhibiting high precision and low area penalty. The A/D converter includes a pipeline stage, and an error correction circuit for performing error correction processing on bit data provided by each stage and generating an n-bit digital signal.    [Non-Patent Document 1] Bang Sup Song, Michael F. Tompsett, and Kadaba R. Lakshmikumar, “A 12 bit 1 M sample/s capacitor error averaging pipelined A/D converter,” IEEE Journal of Solid State Circuits, vol. 23, pp. 1324-1333, Dec. 1988.    [Non-Patent Document 2] You Chiu, “Inherently linear capacitor error-averaging techniques for pipelined A/D converters,” IEEE Trans. Circuits and Systems II, vol. 47, no. 3, pp. 229-232, 2000.    [Non-Patent Document 3] H. S. Chen, K. Bacrania, B. S. Song, “A 14b 20M Sample/s CMOS pipelined ADC,” Deg. Tech. Papers, IEEE Int. Solid-State Circuits Conf., pp. 46-47, 2000.    [Patent Document 1] U.S. Pat. No. 5,510,789    [Patent Document 2] Japanese Unexamined Patent Application Publication 2004-343163    [Patent Document 3] Japanese Unexamined Patent Application Publication 2005-72844